The subject matter disclosed herein relates to memory, and more particularly to the use of a memory circuit using resistive random access memory arrays in a secure element.
Many different types of memory circuits can be used to compare input data (e.g., an input pattern or search data) against stored data (e.g., reference pattern(s) or a table of stored data). One example of such a memory circuit is a Content Addressable Memory (CAM). When a CAM determines a match between the input data and the stored data, it returns the address(es) of the matching data.
A two-state CAM (or Binary CAM (BCAM)) uses binary data consisting entirely of two states (0s and 1s) for comparing input data to stored data as shown in the exemplary two-state CAM truth table of FIG. 1A. The two-state CAM truth table (FIG. 1A) is of an XOR gate (Exclusive OR), wherein the output is “yes” for a match only if both the input state and the stored state are the same. Conversely, the output is a “no” for a mismatch if the input state does not match the stored state.
A three-state CAM (or Ternary CAM (TCAM)) uses data consisting of 0s and 1s as well as a third state known as a “no care” state (or “BX” state) as shown in the exemplary three-state truth table of FIG. 1B. The TCAM truth table (FIG. 1B) is also of an XOR gate (Exclusive OR), wherein the output is “yes” for a match only if (a) the input state and the stored state are the same, (b) the stored state is a “no care” state (BX) regardless of the input state (0, 1, or BX), or (c) the input state is a “no care” state (BX) regardless of the stored state (0, 1, or BX). Conversely, the output is a “no” for a mismatch if the input state does not match the stored state, except in the case where the input state or the stored state is a “no care” state (BX). In many cases, the input data is a stream of several bits, where each input bit must be compared to a stored bit in a CAM cell to determine if all of the bits match to provide a “yes” output.
Most conventional CAMs are built with static random access memory (SRAM) cells or Flash Negative-AND (NAND) cells, where a typical two-state CAM consists of two cells/bit and a typical three-state CAM consists of four cells/bit. Given the high speed of the cells, conventional CAMs allow for stored of information that can be retrieved rapidly. However, SRAMs and Flash cells operate at high power and can be expensive to produce. In addition, conventional CAM arrays for handling multiple bits are manufactured with the control circuitry (e.g., comparators) for comparing the input data and the stored data within the array, increasing the complexity and cost of the memory circuits, while restricting the flexibility of the CAM arrays.
While SRAM, Flash, and other type of memory cells have states that are determined by charge or voltage levels (high (“1”) or low (“0”)), another type of non-volatile memory cell known as Resistive Random Access Memory (referred to as Resistive RAM, RRAM, or ReRAM) have states determined by the resistance level (high or low) and do not trap charges. For example, an electric current can be applied to a ReRAM cell and change the resistance of the material in the cell, which resistance can then be measured, and a “0” (low resistance) or a “1” (high resistance) state can be read. Presently, there are several types of ReRAM that have been introduced, including phase change memories (PCM), conductive bridge random access memory (CBRAM), and metal oxide ReRAMs.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.